Getting Clocking Block SystemVerilog to Work for You
If you've ever dealt with race conditions while writing a testbench, you've probably realized how much a clocking block systemverilog setup can save your sanity. Honestly, there is nothing more frustrating than spending hours debugging a simulation only to realize that your signal changed at the exact same picosecond it was supposed to be sampled. It looks right on the waveform, but the testbench sees the "old" value or the "new" value depending on how the simulator feels that day. That's where the clocking block comes in to save the day. ...